論文誌
国際学会
査読付き国内学会
国内学会・研究会
講演
報道発表
受賞

1.
熊木武志, "高性能CAMベースマルチメディア処理LSIアーキテクチャの研究,"
博士学位論文, Dec., 2006.

2.
熊木武志, 岩井啓介, 黒川恭一, "フレキシブルマルチポート連想メモリ,"
電子情報通信学会論文誌 (D), vol. J87-D-I, no. 1, pp. 12-21, Jan., 2004.

3.
Takeshi Kumaki, Keisuke Iwai and Takakazu Kurokawa, "A flexible multiport content-addressable memory,"
Systems and computers in Japan, vol. 37, no. 11, pp. 57-67, Oct., 2006.

4.
T. Kumaki, Y. Kuroda, M. Ishizaki, T. Koide, H. J. Mattausch, H. Noda, K. Dosaka, K. Arimoto and K. Saito, "Real-time Huffman encoder with pipelined CAM-based data path and code-word-table optimizer,"
IEICE Transactions on Information & Systems, vol. 37, no. 11, pp. 57-67, Jan., 2007.

5.
T. Kumaki, Y. Kono, M. Ishizaki and T. Koide and H. J. Mattausch, "Scalable FPGA/ASIC implementation architecture for parallel table-lookup-coding using multi-ported content addressable memory,"
IEICE Transactions on Information & Systems, vol. E90-D, no. 1, pp. 346-354, Jan., 2007.

6.
T. Kumaki, M. Ishizaki, T. Koide, H. J. Mattausch, Y. Kuroda, H. Noda, K. Dosaka, K. Arimoto and K. Saito, "Acceleration of DCT processing with massive-parallel memory-embedded SIMD matrix processor,"
IEICE Transactions on Information & Systems, vol. E90-D, no. 8, pp. 1312-1315, Aug., 2007.

7.
T. Kumaki, M. Ishizaki, T. Koide, H. J. Mattausch, Y. Kuroda, T. Gyohten, H. Noda, K. Dosaka, K. Arimoto and K. Saito, "Integration architecture of content addressable memory and massive-parallel memory-embedded SIMD matrix for versatile multimedia processor,"
IEICE Transactions on Electronics, vol. E91-C, no. 9, pp. 1409-1418, Sept., 2008.

8.
Takeshi Kumaki, Tetsushi Koide, Hans Juergen Mattausch, Masaharu Tagami, and Masakatsu Ishizaki, "Software-Based parallel cryptographic solution with massive-parallel memory-embedded SIMD matrix architecture for data-storage systems,"
IEICE Transactions on Information & Systems, vol. E94-D, no. 9, pp. 1742-1754, Sept., 2011.

9.
Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Takayuki Gyoten, Tetsu Nishijima, Hiroyuki Yamasaki, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Yoshihiro Okuno, Tetsushi Koide, Hans Juergen Mattausch, and Kazutami Arimoto, "A scalable massively parallel processor for real-time image processing,"
IEEE J. Solid-State Circuits, vol. 46, no. 10, pp. 2363-2373, Oct., 2011.

10.
Takeshi Kumaki, Masahiro Osawa, Syuhe Itaya, Takeshi Ogura, and Takeshi Fujino, "Decomposition/Reconstruction acceleration of max-plus algebra-based morphological wavelet transform with massive-parallel SIMD matrix mobile processor,"
Journal of Signal Processing, vol. 15, no. 6, pp. 425-434, Nov., 2011.

11.
望月陽平, 吉田直之, 松本直樹, 村上佑馬, 熊木武志, 藤野　毅, "SIMD型組込みプロセッサによる疑似乱数生成アルゴリズムの並列処理実装とその評価,"
電子情報通信学会論文誌 (D), vol. J95-D, no. 3, pp. 376-386, Mar., 2012.

12.
Takeshi Kumaki, Yuma Murakami, Syuhe Itaya, Kei Nakao, Takeshi Ogura, and Takeshi Fujino, "Max-plus algebra-based morphological wavelet transform watermarking for highly-parallel processing with mobile embedded processor,"
Journal of Signal Processing, vol. 16, no. 6, pp. 547-556, Nov., 2012.

13.
本多隼也, 望月陽平, 熊木武志, 藤野　毅, "ストリーム暗号CryptMTのデータ並列処理による高速化手法及びSIMD型組み込みプロセッサによる実装と評価,"
電子情報通信学会論文誌 (D), vol. J96-D, no. 3, pp. 495-505, Mar., 2013.

14.
Yuma Murakami, Toshiya Honda, Yuki Yanagihara, Takeshi Kumaki, Takeshi Ogura, and Takeshi Fujino, "Morphological pattern spectrum-based objects detection for protecting privacy,"
Journal of Signal Processing, vol. 17, no. 4, pp. 155-158, Jul., 2013.

15.
Takeshi Kumaki, Tomohiro Fujita, Mamoru Nakanishi, and Takeshi Ogura, "Morphological pattern spectrum and block cipher processing based image-manipulation detection,"
IEICE Transactions on Nonlinear theory and its applications, vol. 4, no. 4, pp. 400-418, Oct., 2013.

16.
Takeshi Kumaki, Kei Nakao, Kohei Hozumi, Takeshi Ogura, and Takeshi Fujino, "Development of compression tolerable and highly implementable watermarking method for mobile devices,"
IEICE Transactions on Information & Systems, vol. E97-D, no. 3, pp. 593-596, Mar., 2014.

17.
Sho Sawada, Tomohiro Fujita, Kaihei Iwanaga, Takeshi Kumaki, Mamoru Nakanishi, and Takeshi Ogura, "A method using CA-based pixel-level snakes for multiple-countour expantion,"
Journal of Signal Processing, vol. 18, no. 4, pp. 221-224, Jul., 2014.

18.
熊木武志，塚田靖史，吉川雅弥，小倉　武，藤野　毅, "ハードウェアトロイ検証環境の開発と暗号回路を用いた実装及び評価,"
電子情報通信学会論文誌 (A), vol. J98-A, no. 4, pp. 313-326, Apr., 2015.

19.
Kyosuke Kageyama, Takeshi Kumaki, Takeshi Ogura, and Takeshi Fujino, "Digital image forensics using morphological pattern spectrum,"
Journal of Signal Processing, vol. 19, no. 4, pp. 159-162, Jul., 2015.

20.
Takeshi Kumaki, Yuri Tanito, Tatsuki Tokunaga, and Takeshi Ogura, "Adaptive multi-directional max-plus algebra-based morphological wavelet transform,"
Journal of Signal Processing, vol. 20, no. 1, pp. xxx-xxx, Jan., 2016.

21.
Lin Meng, Kosaku Fukuda, Takeshi Kumaki, and Takeshi Ogura, "An optical CAM-based separated BTB for a superscalar processor,"
International Journal of Computer Theory and Engineering, vol. 8, no. 2, pp. 122-128, Apr., 2016.

22.
Takeshi Kumaki, Tetsushi Koide, and Takeshi Fujino, "Secure data processing with massive-parallel SIMD matrix for embedded SoC in digital-convergence mobile devices,"
IEEJ Transactions on Electrical and Electronic Engineering, vol. 12, no. 1, pp. xxx-xxx, Jan., 2017.

1.
T. Kumaki, K. Iwai and T. Kurokawa, "A proposal of MFMCAM and its applications,"
International Technical Conference on Circuits/Systems, Computers and communications (ITC-CSCC), 2002.

2.
T. Kumaki, Y. Kuroda, T. Koide, H. J. Mattausch, H. Noda, K. Dosaka, K. Arimoto and K. Saito, "CAM-based VLSI architecture for Huffman coding with real-time opti-mization of the code word table,"
International Symposium on Circuits And Systems (ISCAS), 2005.

3.
T. Kumaki, Y. Kuroda, T. Koide, H. J. Mattausch, H. Noda, K. Dosaka, K. Arimoto and K. Saito, "Multi-port CAM based VLSI architecture for Huffman coding with real-time optimized code word table,"
International MidWest Symposium on Circuits And Systems (MWSCAS), 2005.

4.
Y. Kuroda, T. Kumaki, T. Koide, H.J. Mattausch, H. Noda, K. Dosaka, K. Arimoto and K. Saito, "Highly parallel Huffman encoding by exploiting multiple-matches in content addressable memory,"
International SoC Design Conference (ISOCC), 2005.

5.
M. Ishizaki, T. Kumaki, Y. Kouno, T. Koide, H.J. Mattausch, Y. Kuroda, T. Gyoten, H. Noda, K. Dosaka, K. Arimoto and K. Saito, "Huffman encoding architecture with self-optimizing performance and multiple CAM-match utilization,"
IEEE TENCON, 2006.

6.
T. Kumaki, Y. Kono, M. Ishizaki, T. Koide and H. J. Mattausch, "Application of multi-ported CAM for parallel coding,"
IEEE Asia pacific Conference on Circuits and Systems (APCCAS), 2006.

7.
T. Kumaki, M. Ishizaki, T. Koide, H. J. Mattausch, Y. Kuroda, H. Noda, K. Dosaka, K. Arimoto and K. Saito, "Efficient vertical/horizontal-space 1D-DCT processing based on massive-parallel matrix-processing engine,"
IEEE International Symposium on Circuits And Systems (ISCAS), 2007.

8.
T. Kumaki, Y. Kono, M. Ishizaki, M. Tagami, T. Koide, H. J. Mattausch, T. Gyohten, H. Noda, Y. Kuroda, K. Dosaka, K. Arimoto and K. Saito, "CAM enhanced super parallel SIMD processor with high-speed pattern matching capability,"
IEEE International MidWest Symposium on Circuits And Systems (MWSCAS), 2007.

9.
T. Kumaki, M. Ishizaki, M. Tagami, T. Koide and H. J. Mattausch, "An effective parallel coding architecture utilizing characteristics of multimedia application,"
Synthesis And System Integration of Mixed Information technologies (SASIMI), 2007.

10.
M. Tagami, M. Ishizaki, T. Kumaki, Y. Kono, T. Koide, H. J. Mattausch, T. Gyohten, H. Noda, K. Dosaka, K. Arimoto and K. Saito, "Acceleration of Advanced Encryption Standard (AES) processing on a CAM enhanced super parallel SIMD processor,"
Synthesis And System Integration of Mixed Information technologies (SASIMI), 2007.

11.
T. Kumaki, M. Tagami, Y. Imai, T. Koide and H. J. Mattausch, "A ternary multi-ported content addressable memory architecture utilizing asynchronous multiple search-operation technology,"
Synthesis And System Integration of Mixed Information technologies (SASIMI), 2009.

12.
Y. Imai, T. Kumaki, T. Koide and H. J. Mattausch, "High-Speed face detection in images with massive-parallel bit-serial SIMD processor using Haar-Like features,"
Solid State Devices and Materials (SSDM), 2009.

13.
T. Kumaki, Y. Imai, T. Koide and H. J. Mattausch, "VLSI-architecture for enabling multiple parallel associative searches with standard SRAM macros,"
International Symposium on Intelligent Signal Processing And Communication Systems (ISPACS), 2009.

14.
T. Kurafuji, M. Haraguchi, M. Nakajima, T. Gyoten, T. Nishijima, H. Yamasaki, Y. Imai, M. Ishizaki, T. Kumaki, T. Koide, H. J. Mattausch and K. Arimoto, "A 310GOPS/W and 36.1GOPS/mm2 scalable massively parallel processor for real-time image processing SoC,"
International Solid State Circuits Conference (ISSCC), 2010.

15.
T. Kumaki, Y. Imai, H. Hiramoto, T. Koide, and H. J. Mattausch, "Realization of efficient and low-power parallel face-detection with massive-parallel memory-embedded SIMD matrix,"
International MidWest Symposium on Circuits And Systems (MWSCAS), 2010.

16.
Z. B. Rafi'i, T. Kumaki, T. Fujita, M. Nakanishi, and T. Ogura, "Real-Time morphological pattern spectrum analyzer on cellu-lar-automata hardware platform,"
RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 2011.

17.
M. Nakai, S. Shirai, T. Kumaki, T. Fujita, M. Nakanishi, and T. Ogura, "Reconstruction of morphological wavelet transform on cellular automata hardware platform,"
RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 2011.

18.
T. Kumaki, M. Osawa, S. Itaya, T. Ogura, and T. Fujino, "Decomposition/Reconstruction processing of max-plus algebra-based morphological wavelet transform with massive-parallel SIMD matrix architecture,"
RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 2011.

19.
T. Kumaki, H. Yoshikawa, Y. Kurokawa, and T. Fujino, "Highly-Parallel bitslice AES implementation with massive-parallel SIMD matrix for mobile processor,"
International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), 2011.

20.
H. Hiramoto, T. Koide, H. J. Mattausch, and T. Kumaki, "Application of composite Haar-like features to face detection with massive-parallel memory-embedded SIMD matrix processor,"
International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), 2011.

21.
S. Shirai, M. Nakai, T. Kumaki, T. Fujita, M. Nakanishi, and T. Ogura, "Morphological wavelet transform using multiple direction sampling windows on cellular hardware platform,"
IEEE International NEW Circuits And Systems conference (NEWCAS), 2011.

22.
M. Nawata, S. Shirai, M. Nakai, T. Kumaki, T. Fujita, and T. Ogura, "Compression efficiency study of directional morphological wavelet transform,"
RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 2012.

23.
Y. Murakami, M. Osawa, S. Itaya, N. Matsumoto, K. Nakao, T. Kumaki, T. Ogura, and T. Fujino, "Highly-Parallel watermarking implementation for max-plus algebra morphological wavelet transform with massive-parallel SIMD matrix evaluation board,"
RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 2012.

24.
Z. B. Rafi'i, T. Kumaki, T. Fujita, M. Nakanishi, and T. Ogura, "Implementation results and application of real-time morphological pattern spectrum analyzer on cellular-automata hardware,"
RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 2012.

25.
Y. Tsuji, T. Fujita, T. Matsui, T. Kumaki, M. Nakanishi, and T. Ogura, "An implementation of pixel level snake to cellular hardware platform,"
RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 2012.

26.
H. Yoshikawa, T. Kumaki, and T. Fujino, "Highly-Parallel AES processing for five confidentiality modes with massive-parallel SIMD matrix processor,"
Synthesis And System Integration of Mixed Information technologies (SASIMI), 2012.

27.
L. Meng, T. Kumaki, K. Yamazaki, T. Ogura, and S. Oyanagi, "A branch address predictor for reducing the BTB miss by using CAM,"
IEEE symposium on low-power and high-speed chips (Cool Chips), 2012.

28.
T. Takeda, T. Kumaki, and T. Fujino, "Highly-Parallel triple DES processing with massive-parallel SIMD matrix evaluation board,"
International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), 2012.

29.
T. Kumaki, Z. B. Rafi'i, T. Fujita, M. Nakanishi and T. Ogura, "Morphological pattern spectrum-based image manipulation detector,"
International symposium on Nonlinear and its Applications (NOLTA), 2012.

30.
M. Yoshikawa, R. Satoh and T. Kumaki, "Hardware Trojan for security LSI,"
IEEE International conference on Consumer Electronics (ICCE), 2013.

31.
M. Yoshikawa, T. Tsukadaira and T. Kumaki, "Trojan circuit for countermeasures against fault analysis attacks,"
World Academy of Science, Engineering and Technology, 2013.

32.
Y, Tanito, T. Tokunaga, M. Nawata, T. Kumaki, T. Fujita, and T. ogura, "Adaptive multi-directional morphological wavelet transform and it's compression efficiency,"
RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 2013.

33.
Y. Murakami, T. Honda, Y. Yanagihara, T. Kumaki, T. Ogura and T. Fujino, "Use of morphological pattern spectrum to detect objects and protect privacy,"
RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 2013.

34.
T. Honda, K. Nakagawa, T. Kumaki, M. Kimata and T. Fujino, "Development of low-power camera sensor node using infrared array sensor and CMOS image sensor,"
RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 2013.

35.
R. Hori, K. Nakagawa. T. Honda, T. Kumaki and T. Fujino, "Low power sensor system using smart analog under normally off operation,"
RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 2013.

36.
T. Matsui, T. Fujita, Y. Tsuji, T. Kumaki, M. Nakanishi and T. Ogura, "Evaluation of advanced pixel-level snakes on cellular hardware plat-form,"
IEEE International NEW circuit and systems conference on Circuits And Systems (NEWCAS), 2013.

37.
T. Kumaki, M. Yoshikawa and T. Fujino, "Cipher-destroying and secret-key-emitting hardware Trojan against AES core,"
IEEE International MidWest Symposium on Circuits And Systems (MWSCAS), 2013.

38.
K. Nakao, K. Hozumi, T. Kumaki, T. Ogura and T. Fujino, "Development of effective information-hiding method for embedded systems,"
IEEE International MidWest Symposium on Circuits And Systems (MWSCAS), 2013.

39.
T. Honda, Y. Murakami, Y. Yanagihara, T. Kumaki and T. Fujino, "Hierarchical image-scrambling method with scramble-level controllability for privacy protection,"
IEEE International MidWest Symposium on Circuits And Systems (MWSCAS), 2013.

40.
M. Yoshikawa, Y. Mori and T. Kumaki, "Implementation aware Hardware Trojan Trigger,"
International Conference on Industrial Electronics and Applications, 2014.

41.
M. Yoshikawa, D. Takeuchi and T. Kumaki, "Reset Siganal Aware Hardware Trojan Trigger,"
International Conference on Advances in Engineering and Technology, 2014.

42.
S. Sawada, T. Fujita, K. Iwanaga, T. Kumaki, M. nakanishi and T. Fujino, "Multiple contour expamsion method by CA based pixel level snakes,"
RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 2014.

43.
T. Tokunaga, Y. Tanito, T. Kumaki, T. Fujita and T. Fujino, "L2 decomposition of adaptive directional morphological wavelet transform,"
RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 2014.

44.
T. Honda, K. Nakagawa, Y. Yanagihara, T. Kumaki, M. Kimata and T. Fujino, "Lightweight privacy protection in intermittent-sensing image sensor node,"
RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 2014.

45.
S. Fujimoto, T. Honda, T. Kumaki, M. Kimata and T. Fujino, "Human detection algorithm using low-resolution infrared image in wireless sensor networks,"
RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 2014.

46.
K. Nakao, T. Kumaki, T. Ogura and T. Fujino, "A cropping robust digital watermarking algorithm using morphological wavelet transform based on max-plus algebra,"
RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 2014.

47.
T. Hitomi, T. Honda, R. Hori, T. Kumaki and T. Fujino, "Hardware controller of camera sensor node using IR array sensor and CMOS image sensor for ultra-low-power operation,"
RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 2014.

48.
Y. Yanagihara, T. Honda, T. Kumaki and T. Fujino, "Live demonstration: Hierarchical masked image filtering technology on security-camera privacy protection,"
IEEE International Symposium on Circuits And Systems (ISCAS), 2014.

49.
T. Kumaki, T. Fujino and T. Koide, "Interleaved-bitslice AES encryption and decryption with massive-parallel mobile embedded processor,"
IEEE Asia pacific Conference on Circuits and Systems (APCCAS), 2014.

50.
T. Hitomi, S. Ueguchi, T. Kumaki and T. Fujino, "The Intermittent-Operation Control LSI for Ultra-Low-Power Camera: Green Smart Secure Eyes,"
RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 2015.

51.
K. Kageyama, T. Kumaki and T. Fujino, "Morphological Pattern Spectrum-based Image Manipulation Detection,"
RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 2015.

52.
Y. Tsukada, T. Kumaki, M. Yoshikawa and T. Fujino, "Attack alert circuit for hardware Trojan in the embedded system,"
RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 2015.

53.
K. Ueda, M. Ikeda, T. Kumaki and T. Ogura, "Adaptive multi-directional image reduction method,"
RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 2015.

54.
K. Abe, M. Ikeda, T. Kumaki and T. Ogura, "Method for expanding adaptive multi-directional images,"
RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 2015.

55.
M. Ikeda, T. Kumaki and T. Ogura, "An embedding method using morphological wavelet transform based on max-plus algebra for digital watermarking,"
RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 2015.

56.
K. Kageyama, K. Sugiyama, T. Kumaki and T. Fujino, "Proposal of LED-based peeping prevention system,"
IEEE International MidWest Symposium on Circuits And Systems (MWSCAS), 2015.

57.
K. Kageyama, K. Sugiyama, T. Kumaki and T. Fujino, "Development of LED illumination-based spy photo-prevention system,"
IEEE Global Conference on Consumer Electronics (GCCE), 2015.

58.
R. Yukawa, T. Kumaki, T. Fujita, and T. Ogura, "Ternary Content Addressable Memory with Individuality on FPGA,"
International symposium on Nonlinear and its Applications (NOLTA), 2015.

59.
Y. Hioki, T. Kumaki, T. Fujita, and T. Ogura, "Cellular hardware platform: CAM^2 on FPGA,"
International symposium on Nonlinear and its Applications (NOLTA), 2015.

60.
S. Nishida, T. Kumaki, T. Fujita and T. Ogura, "Implementation of cellular automata based pixel-level snakes on CAM^2,"
RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 2015.

61.
Y. Nakashima, Y. Mizuno, T. Kumaki and T. Fujino, "Morphological pattern spectrum-based image manipulation detection for compression data,"
RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 2016.

62.
S. Ueguchi, M. Nagao, T. Kumamoto, M. Shirahata, T. Kumaki and T. Fujino, "Design of low power AFE circuit supporting IR array sensor for human detection,"
RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 2016.

63.
S. Kimura, T. Watanabe, R. Yukawa, T. Kumaki, T. Fujita and T. Ogura, "Evaluation of ternary content addressable memory with individuality on FPGA,"
RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 2016.

64.
M. Ikeda, T. Kumaki and T. Ogura, "A transcoding method of MPEG-2 to HEVC with picture structure information,"
RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 2016.

65.
K. Sugiyama, K. Kageyama, T. Kumaki and T. Fujino, "Information including flicker noise with LED lighting for preventing spy-photos,"
RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 2016.

66.
K. Kageyama, K. Sugiyama, T. Kumaki and T. Fujino, "1/f fluctuation-based visible light beacon for spy-photo prevention system,"
RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 2016.

67.
M. Nagao, S. Ueguchi, T. Kumaki, M. Shirahata, T. Kumamoto and T. Fujino, "Study of human event detection algorithm by infrared array sensor on low power consumption image sensor node,"
RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 2016.

1.
望月陽平, 吉田直之, 松本直樹, 村上佑馬, 熊木武志, 藤野　毅, "マトリクスアーキテクチャ型超並列演算プロセッサを用いたMersenne twisterの並列処理実装とその評価, "
第10回情報科学技術フォーラム (FIT2011), pp. 67-74, Sep., 2011.

1.
熊木武志, 岩井啓介, 黒川恭一, "多機能マルチポートCAMとその応用例, "
情報処理学会第64回全国大会, Vol. 1, pp. 55-56, Mar., 2001.

2.
熊木武志, 岩井啓介, 黒川恭一, "改良型多機能マルチポートCAMの提案, "
Forum on Information Technology 2002 (FIT2002), Vol. 1, No. C-9, pp. 205-206, Sept., 2002.

3.
熊木武志, 岩井啓介, 黒川恭一, "FMCAMのIPルータへの適用, "
防衛大学校理工学研究報告, Vol. 41, No. 2, pp. 31-38, Mar., 2003.

4.
T. Kumaki, Y. Kuroda, M. Ishizaki, T. Koide and H. J. Mattausch, "CAM-Based Huffman Coding Architecture for Real-Time Applications, "
21st COE program, The Fourth Hiroshima International Workshop on Nanoelectronics for Tera-Bit Information Processing, Sept., 2005.

5.
T. Kumaki, Y. Kono, M. Ishizaki, T. Koide and H. J. Mattausch, "Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-word-table Optimizer, "
21世紀COEプログラム「テラビット情報ナノエレクトロニクス」　広島大学半導体技術シンポジウム, June, 2006.

6.
幸野　豊, 熊木武志, 石崎雅勝, 田上正治, 小出哲士, マタウシュ ハンス ユルゲン, 行天隆幸, 野田英行, 黒田泰斗, 堂坂勝己, 有本和民, 齊藤和則, "CAMによる高速パターンマッチング機能を有する超並列SIMDプロセッサ, "
信学技報, ICD2006-116, pp. 34-44, Oct. 2006.

7.
石崎雅勝, 熊木武志, 幸野　豊, 田上正治, 小出哲士, マタウシュ ハンス ユルゲン, 黒田泰斗, 行天隆幸, 野田英行, 堂坂勝己, 有本和民, 齊藤和則, "
マルチプルCAMマッチとアダプティブテーブル最適化を利用するリアルタイムハフマン符号化アーキテクチャ, 信学技報, ICD2006-165, pp. 125-130, Dec. 2006.

8.
T. Kumaki, Y. Kono, M. Ishizaki, T. Koide and H. J. Mattausch, "Highly-Parallel table-Lookup-Coding with Scalable Architecture using Flexible Multi-Ported Content Addressable Memory, "
21st COE program, The Fifth Hiroshima International Workshop on Nanoelectronics for Tera-Bit Information Processing, Jan., 2007.

9.
田上正治, 熊木武志, 幸野　豊, 石崎雅勝, 小出哲士, マタウシュ　ハンス　ユルゲン, "超並列SIMDプロセッサによる暗号化 (AES)処理の一手法, "
2007年電子情報通信学会総合大会, pp. 88, Mar., 2007.

10.
田上正治, 石崎雅勝, 熊木武志, 幸野　豊, マタウシュ　ハンス　ユルゲン, "CAMを付加した超並列SIMDプロセッサによるAES処理高速化手法 (1)〜暗号化方法〜, "
平成19年度電気・情報関連学会中国支部第58回連合大会, pp. 93-94, Oct., 2007.

11.
石崎雅勝, 田上正治, 熊木武志, 幸野　豊, 小出哲士, マタウシュ　ハンス　ユルゲン, "CAMを付加した超並列SIMDプロセッサによるAES処理高速化手法 (2)〜復号化方法〜, "
平成19年度電気・情報関連学会中国支部第58回連合大会, pp. 95-96, Oct., 2007.

12.
熊木武志, 石崎雅勝, 田上正治, 今井雄太, 小出哲士, マタウシュ　ハンス　ユルゲン, "マルチポート連想メモリを用いた効果的な並列符号化処理について, "
平成19年度電気・情報関連学会中国支部第58回連合大会, pp. 322-323, Oct., 2007.

13.
熊木武志, 石崎雅勝, 田上正治, 小出哲士, マタウシュ　ハンス　ユルゲン, "CAMを有する超並列SIMD型演算プロセッサによる効果的なマルチメディアデータ処理について, "
信学技報, CPSY2007-27, pp. 19-24, Oct., 2007.

14.
石崎雅勝, 熊木武志, 田上正治, 小出哲士, マタウシュ　ハンス　ユルゲン, "CAMを有する超並列SIMD型演算プロセッサによる効果的なAES暗号化処理, "
信学技報, CPSY2007-28, pp. 25-30, Oct., 2007.

15.
熊木武志, 田上正治, 今井雄太, 小出哲士, マタウシュ　ハンス　ユルゲン, "超並列SIMD型演算プロセッサMX-1を用いた並列顔検出処理手法 (1), "
2008年電子情報通信学会ソサイエティ大会, C-12-30, Sept., 2008.

16.
今井雄太, 熊木武志, 田上正治, 小出哲士, マタウシュ　ハンス　ユルゲン, "超並列SIMD型演算プロセッサMX-1を用いた並列顔検出処理手法 (2), "
2008年電子情報通信学会ソサイエティ大会, C-12-31, Sept., 2008.

17.
田上正治, 熊木武志, 今井雄太, 小出哲士, マタウシュ　ハンス　ユルゲン, "超並列SIMD型演算プロセッサMX-1への暗号化処理の実装, "
2008年電子情報通信学会ソサイエティ大会, C-12-32, Sept., 2008.

18.
小出哲士, 熊木武志, マタウシュ　ハンス　ユルゲン, "超並列メモリエンベディッドSIMD型プロセッサアーキテクチャ, "
信学技報, vol. 109, no. 199, pp. 59-64, Sep., 2009.

19.
熊木武志, 今井雄太, 小出哲士, マタウシュ　ハンス　ユルゲン, "3値多ポート連想メモリの開発とその応用例, "
信学技報, vol. 109, no. 199, pp. 97-102, Sep., 2009.

20.
今井雄太, 熊木武志, 平本寛和, 小出哲士, マタウシュ　ハンス　ユルゲン, "超並列SIMD型演算プロセッサMX-1による並列顔検出処理, "
the 11th IEEE Hiroshima student symposium, Nov., 2009.

21.
平本寛和, 熊木武志, 今井雄太, 小出哲士, マタウシュ　ハンス　ユルゲン, "超並列SIMD型プロセッサMX-1のための改良顔検出手法, "
信学技報, vol. 109, no. 336, pp. 83-88, Dec., 2009.

22.
吉田直之, 松本直樹, 熊木武志, 藤野 毅, "超並列SIMD 型演算プロセッサMX-1 へのMersenneTwister の実装 (1), "
2010 年電子通信情報学会ソサイエティ大会, A-1-1, Aug. , 2010.

23.
松本直樹, 吉田直之, 熊木武志, 藤野 毅, "超並列SIMD 型演算プロセッサMX-1 へのMersenneTwister の実装 (2), "
2010 年電子通信情報学会ソサイエティ大会, A-1-2, Aug. , 2010.

24.
吉川弘起, 黒川悠一郎, 熊木武志, 藤野　毅, "超並列SIMD型演算プロセッサMX-1のためのガロア体演算によAES用SubBytes変換の高速化, "
2010 年電子通信情報学会ソサイエティ大会, A-1-3, Aug. , 2010.

25.
中井真樹, 白井将太, 熊木武志, 小倉　武, "セルラ型ハードウェアのための並列モルフォロジカルウェーブレット変換処理アルゴリズム, "
平成22年度情報処理学会関西支部大会, Sep., 2010.

26.
白井将太, 中井真樹, 熊木武志, 小倉　武, "セルラ型ハードウェアを用いた並列モルフォロジカルウェーブレット変換処理の実装と評価, "
平成22年度情報処理学会関西支部大会, Sep., 2010.

27.
吉川弘起, 本田　弘, 熊木武志, 藤野　毅, "超並列SIMDプロセッサMX-1を用いたAES暗号の高速処理実装, "
The 28th Symposium on Cryptography and Information Security (SCIS), Jan., 2011.

28.
板屋修平, 大澤昌弘, 熊木武志, 小倉　武, 藤野　毅, "マックスプラス代数系に基づくモルフォロジカル・ウェーブレット変換を用いた電子透かしの実装及び評価, "
信学技報, vol. 110, no. 457, pp. 219-224, Feb., 2011.

29.
大澤昌弘, 板屋修平, 熊木武志, 藤野　毅, "超並列SIMD型演算プロセッサをMX-1によるモルフォロジカルウェーブレット変換処理の実装, "
情報処理学会第73回全国大会, Mar., 2011.

30.
望月陽平, 吉田直之, 松本直樹, 村上佑馬, 熊木武志, 藤野　毅, "超並列処理を用いた疑似乱数生成アルゴリズムMersenneTwisterの実装及び評価, "
信学技報, vol. 110, no. 473, pp. 273-278, Mar., 2011.

31.
熊木武志, 黒川悠一朗, 藤野　毅, "超小型組込みボードを用いた暗号処理の並列化に関する研究, "
信学技報, vol. 110, no. 473, pp. 279-284, Mar., 2011.

32.
本多隼也, 村上佑馬, 熊木武志, 藤野　毅, "プライバシー保護のための閲覧者権限に応じた画像フィルタリング手法の提案, "
Forum on Information Technology 2011 (FIT2011), N-036, Sept., 2011.

33.
村上佑馬, 本多隼也, 熊木武志, 藤野　毅, "プライバシー保護のための閲覧者権限に応じた画像フィルタリング手法の実装と評価, "
Forum on Information Technology 2011 (FIT2011), N-036, Sept., 2011.

34.
辻　雄爾, 藤田智弘, 松井孝夫, 熊木武志, 中西　衛, 小倉　武, "ピクセルレベルスネークスのセルラーハードウェアプラットフォームへの実装法, "
信学技報, no. FIIS-11-313, Nov., 2011.

35.
熊木武志, 望月陽平, 藤野　毅, "暗号処理用LSIに組み込まれたハードウェアトロイに関する研究, "
信学技報, vol. 111, no. CPSY-328, pp. 21-26, Nov., 2011.

36.
熊木武志, 望月陽平, 板屋修平, 藤野　毅, "AES暗号回路に組み込まれたハードウェアトロイとその対策回路について, "
The 29th Symposium on Cryptography and Information Security (SCIS), 1C3-1, Jan., 2012.

37.
本多隼也, 村上佑馬, 熊木武志, 藤野　毅, "監視カメラシステムのための画質制御可能な動画像マスク方式, "
The 29th Symposium on Cryptography and Information Security (SCIS), 3E3-2, Jan., 2012.

38.
松井孝夫, 辻　雄爾, 藤田智弘, 熊木武志, 中西　衛, 小倉　武, "セルラーハードウェアプラットフォーム上のピクセルレベルスネークの高度化とその評価, "
信学技報, no. FIIS, Mar., 2012.

39.
中尾　慧, 板屋修平, 大澤昌弘, 熊木武志, 藤野　毅, "組み込み機器における効果的な情報ハイディング手法の検討, "
信学技報 EMM2011-76,, vol. 111, no. 496, pp. 71-76, Mar., 2012.

40.
孟　林, 熊谷友岐, 熊木武志, 山崎勝弘, 小倉　武, 小柳　滋, "分岐予測におけるBTBミスの削減, "
情報処理学会第74回全国大会, Mar., 2012.

41.
吉田将之, 佐藤隆亮, 熊木武志, 吉川雅弥, "対策回路に対するハードウェアトロイの検討, "
Forum on Information Technology 2012 (FIT2012), Sept., pp. 295-296, 2012.

42.
吉田将之, 佐藤隆亮, 熊木武志, 吉川雅弥, "電力解析攻撃対策を無効にするハードウェアトロイの考察, "
電気関係学会東海支部連合大会, Sept., no. A1-7, 2012.

43.
柳原裕樹, 本多隼也, 村上佑馬, 熊木武志, 藤野 毅, "超小型組込みボードを用いた階層型フィルタリング手法の実装と評価, "
2012 年電子通信情報学会ソサイエティ大会, no. A-7-1, Aug. , 2012.

44.
村上佑馬, 竹田知弘, 熊木武志, 藤野 毅, 小倉　武, "モルフォロジカルパターンスペクトラムを用いた検出技術によるプライバシー保護手法の検討, "
2012 年電子通信情報学会ソサイエティ大会, no. A-7-4, Aug. , 2012.

45.
本多隼也, 村上佑馬, 熊木武志, 藤野 毅, "ストリーム暗号CryptMTのデータ並列処理による高速化について, "
2012 年電子通信情報学会ソサイエティ大会, no. A-7-9, Aug. , 2012.

46.
夕川諒平, 熊木武志, 吉川雅弥, 藤野　毅, 小倉　武, "連想メモリを用いたハードウェアトロイ監視回路についての検討, "
2012 年電子通信情報学会ソサイエティ大会, no. C-12-32, Aug. , 2012.

47.
望月陽平, 熊木武志, 吉川雅弥, 藤野　毅, "トリプルDESに組み込まれたハードウェアトロイの試作とその検知手法の検討, "
信学技報, vol. 112, no. CPSY2012-53, pp. 33-38, Nov., 2012.

48.
穂積康平, 中尾　慧, 熊木武志, 小倉　武, 藤野　毅, "モバイル機器向け電子透かしの開発, "
The 29th Symposium on Cryptography and Information Security (SCIS), 3F2-3, Jan., 2013.

49.
塚平峻矢, 松島大祐, 熊木武志, 吉川雅弥, "フォールト解析対策回路を対象としたハードウェアトロイの実装と評価, "
信学技報, vol. 112, no. 451, pp. 141-146, Feb., 2013.

50.
塚田靖史, 竹田知弘, 本多隼也, 熊木武志, 小倉　武, 藤野　毅, "超高速並列演算コアを用いたモルフォロジカルパターンスペクトラムの実装と評価, "
信学技報, vol. 112, no. CPSY-2012-90, pp. 229-234, Mar., 2013.

51.
中川和歩, 堀　遼平, 熊木武志, 木股雅章, 藤野　毅, "センサノード低消費電力化のためのノーマリーオフ動作検証環境の構築と評価, "
信学技報, vol. 112, no. CPSY-2013-481, pp. 211-216, Mar., 2013.

52.
竹田知弘, 塚田靖史, 熊木武志, 小倉　武, 藤野　毅, "モルフォロジカルパターンスペクトラムを用いた検知手法の提案, "
信学技報, vol. 113, no. IE2013-5, pp. 23-28, Apr., 2013.

53.
本多隼也, 中川和歩, 熊木武志, 木股雅章, 藤野　毅, "間歇動作による低消費電力イメージセンサノードの開発と検証, "
Forum on Information Technology 2013 (FIT2013), M-025, Aug., 2013.

54.
柳原裕樹, 本多隼也, 熊木武志, 藤野　毅, "階層型フィルタリング手法を用いた監視カメラデモシステム開発とその評価, "
Forum on Information Technology 2013 (FIT2013), O-025, Aug., 2013.

55.
塚田靖史, 竹田知弘, 本多隼也, 熊木武志, 小倉　武, 藤野　毅, "マトリクスアーキテクチャ型超並列SIMD演算プロセッサを用いたモルフォロジカルパターンスペクトラムの実装と評価, "
Forum on Information Technology 2013 (FIT2013), C-017, Aug., 2013.

56.
塚田靖史, 板屋修平, 熊木武志, 吉川雅弥, 小倉　武, 藤野　毅, "組込みプロセッサに仕掛けられたハードウェアトロイに関する研究, "
信学技報, vol. 113, no. CPSY2013-324, pp. 29-34, Nov., 2013.

57.
蔭山享佑, 本多隼也, 中川和歩, 熊木武志, 藤野　毅, "可視光ビーコンを利用した犯罪防止システムの検討, "
信学技報, vol. 113, no. DC2013-498, pp. 301-306, Mar., 2014.

58.
福田考作, 孟　林, 熊木武志, 小倉　武, "組込みプロセッサ用分離式BTBのFPGA実装と電力評価, "
情処学組込みシステム研報, vol. 2014-EMB-34, no. 2, pp. 1-6, Sept., 2014.

59.
中島圭崇, 塚田靖史, 熊木武志, 吉川雅弥, 藤野　毅, "ハードウェアトロイの特性を利用した盗難防止システムの検討, "
信学技報, vol. 114, no. CPSY2014-346, pp. 29, Nov., 2014.

60.
日置洋祐, 熊木武志, 藤田智弘, 小倉　武, "セルラーハードウェアプラットフォーム: CAM^2のFPGAによる実装と評価, "
信学技報, vol. 114, no. CPSY2014-346, pp. 41, Nov., 2014.

61.
杉山幸平, 蔭山享佑, 熊木武志, 藤野　毅, "LED照明を用いたスマートフォンとの連携による犯罪防止空間の構築, "
信学技報, vol. 114, no. 507, pp. 65-70, Mar., 2015.

62.
熊木武志, 蔭山享佑, 杉山幸平, 藤野　毅, 森　有生, 佐々木文子, "LED照明を利用したスマートフォン盗撮防止システムの開発, "
The 29th Symposium on Cryptography and Information Security (SCIS), 1C2-4, Jan., 2016.

京都産学公連携機構，第4回未来技術交流回，基調講演, Aug., 2014. URL

日本経済新聞, 読売新聞, 京都新聞, 中日新聞, 産経新聞, 朝日新聞, 毎日新聞, 日刊工業新聞, "LED照明とスマホシステムの連携による盗撮防止システムの開発〜スマホ等による盗撮被害を防ぐために〜," 新聞発表, Sep., 2014. 記事

読売テレビ かんさい情報ネット ten, テレビ朝日 グッド！モーニング, "LED照明とスマホシステムの連携による盗撮防止システムの開発〜スマホ等による盗撮被害を防ぐために〜," ニュース報道, Sep., 2014. 動画

テレビ東京 ワールドビジネスサテライト トレンドたまご, "LED照明とスマホシステムの連携による盗撮防止システムの開発〜スマホ等による盗撮被害を防ぐために〜," ニュース報道, Nov., 2014. URL, 動画

1.
幸野　豊，熊木武志，石崎雅勝，田上正治，小出哲士，マタウシュ ハンス ユルゲン，行天隆幸，野田秀行，堂坂勝己，有本和民，齊藤和則, "CAMによる高速パターンマッチング機能を有する超並列SIMDプロセッサ,"
第126回SLDM研究会優秀発表学生賞, Oct., 2006.

2.
第9回LSI IPデザイン・アワード開発奨励賞, Apr., 2007.

3.
財団法人丸文研究交流財団国際交流助成, May, 2007. URL

4.
第10回LSI IPデザイン・アワード開発奨励賞, Apr., 2008.

5.
情報ハイディング及びその評価委員会　第1回電子透かしコンテスト提案技術認定, Sept., 2012. URL

6.
Y. Murakami, T. Honda, Y. Yanagihara, T. Kumaki, T. Ogura and T. Fujino, "Use of morphological pattern spectrum to detect objects and protect privacy,"
Nonlinear circuits, Communications and Signal Processing (NCSP) 2013，Student Paper Award, Mar., 2013.

7.
熊木武志, 竹田知弘, 小倉 武, 藤野 毅, "画像の構造解析に基づいた改ざん検知手法,"
2013年度映像メディア処理シンポジウム (IMPS2013), ベストポスター賞, Nov., 2013.

8.
S. Sawada, T. Fujita, K. Iwanaga, T. Kumaki, M. Nakanishi and T. Ogura, "Multiple contour expansion method by CA based pixel level snakes,"
Nonlinear circuits, Communications and Signal Processing (NCSP) 2014，Student Paper Award, Mar., 2014.

9.
M. Yoshikawa, D. Takeuchi and T. Kumaki, "Reset signal aware hardware Trojan trigger,"
Proc. of International Conference on Advances in Engineering and Technology，Session Best Paper Certificate, Mar., 2014.

10.
T. Kumaki, Y. Murakami, S. Itaya, K. Nakao, T. Ogura, and T. Fujino, "Max-plus algebra-based morphological wavelet transform watermarking for highly-parallel processing with mobile embedded processor,"
Journal of Signal Processing, vol. 16, no. 6, pp. 547-556, Nov., 2012., 第8回信号処理学会論文賞, May, 2014.

11.
蔭山享佑, 熊木武志, 藤野 毅, "可視光ビーコンを利用した犯罪防止システムの実装及び評価,"
LSIとシステムのワークショップ2014，IEEE SSCS Kansai Chapter Academic Research Award, May, 2014.

12.
人見達郎，熊木武志，藤野 毅, "センサ制御機構のハードウェア化による間欠動作イメージセンサノードGSSEの省電力化,"
STARCシンポジウム2015，優秀ポスター賞, Jan., 2015.

13.
K. Kageyama, T. Kumaki, T. Ogura and T. Fujino, "Human-like image manipulation detection using morphological pattern spectrum,"
Nonlinear circuits, Communications and Signal Processing (NCSP) 2015，Student Paper Award, Mar., 2015.

14.
夕川諒平，日置洋佑，熊木武志，藤田智弘，小倉　武 "チップのばらつきを利用してロボットの個性を実現する3値連想メモリの開発,"
第5回VDECデザインアワードアイディアコンテスト部門，VDECデザインアワード嘱望賞, Aug., 2015.

15.
S. Ueguchi, M. Nagao, T. Kumamoto, M. Shirahata, T. Kumaki and T. Fujino, "Design of Low Power AFE Circuit supporting IR Array Sensor for Human Detection,"
Nonlinear circuits, Communications and Signal Processing (NCSP) 2015，Student Paper Award, Mar., 2016.

16.
S. Kimura, T. Watanabe, R. Yukawa, T. Kumaki, T. Fujita and T. Ogura, "Evaluation of Ternary Content Addressable Memory with Individuality on FPGA,"
Nonlinear circuits, Communications and Signal Processing (NCSP) 2015，Student Paper Award, Mar., 2016.